1. Field of the Invention
The present invention relates to large scale and very large scale integrated (LSI/VLSI) circuits, and more particularly to techniques and structures for reducing the resistance of the elements of LSI/VLSI circuits for high speed, high power applications.
2. Description of the Prior Art
No prior art directly specific to the use of buried contacts to reducing the spreading resistance of LSI/VLSI elements can be cited. Background art related to the general technology is as follows:
U.S. Pat. No. 3,964,092 issued June 15, 1976 to Wadham, entitled SEMICONDUCTOR DEVICES WITH CONDUCTIVE LAYER STRUCTURE describes a semiconductor device, for example an integrated circuit comprising insulated gate field effect transistors in which the gate electrodes comprise doped portions of a deposited layer of polycrystalline silicon, wherein a first conductive connection layer extends at least partly on insulating material present on one surface of a semiconductor body, the first layer being insulated from and crossing over an underlying, second conductive connection layer which is of semiconductor material locally deposited on the one surface of the semiconductor body, the second layer and the underlying portion of the semiconductor body comprising a quantity of doping substance introduced via said second layer for example in the case of a silicon gate circuit introduced at the same time as simultaneously doping the gate electrodes and forming the source and drain regions.
U.S. Pat. No. 3,986,903 issued Oct. 19, 1976 to Watrous, Jr., entitled MOSFET TRANSISTOR AND METHOD OF FABRICATION, describes an n channel MOSFET transistor which includes doping of previously formed source and drain elements with a heavy diffusion of phosphorous or arsenic creating n.sup.++ regions in the source and drain. The extra diffusion step is preferably accomplished just prior to contact metallization.
U.S. Pat. No. 4,193,080 issued Mar. 11, 1980 to Koike et al, entitled NON-VOLATILE MEMORY DEVICE describes a memory device of MNOS FET type wherein a high concentration part and a low concentration part contact each other in the source region and the drain region, and further, double layered insulation films under the gate electrode extending across the source region and drain region are made to contact only the lower concentration part, so that an acceptor impurity is prevented from mixing into the double layered insulation films from the source region and drain region, thus greatly improving the life of the device.
U.S. Pat. No. 4,405,935 issued Sept. 20, 1983 to Baji et al, entitled SOLID-STATE IMAGING DEVICE, discloses a solid-state imaging device having a semiconductor integrated circuit in which a plurality of switching elements for selecting positions of picture elements and scanners for turning "on" and "off" the switching elements in time sequence are disposed on an identical substrate, a photoconductive film which is disposed on the integrated circuit and which is connected to one end of each of the switching elements, and a light transmitting electrode which is disposed on the photoconductive film.
U.S. Pat. No. 4,503,448 issued Mar. 5, 1985 to Miyasaka, entitled SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A HIGH TOLERANCE AGAINST ABNORMALLY HIGH INPUT VOLTAGE, describes a semiconductor integrated device with a high tolerance against abnormally high input voltages which comprises a first MIS transistor at the input stage and a second MIS transistor of the internal elements of the device. The source of the first MIS transistor is connected to an input electrode. The drain of the first MIS transistor is connected to the gate of the second MIS transistor. The source region of the first MIS transistor comprises phosphoric atoms. The other diffusion regions comprise arsenic atoms. Therefore, the depth of the source region of the first MIS transistor is greater than the other diffusion region.